1. Field of the Invention
The present invention relates generally to microprocessors and methods for reducing leakage power.
2. Description of the Related Art
Recently, it has been a concern to reduce power dissipation for microprocessors, which is currently being investigated in the field. As attempts are made to reduce unnecessary power dissipation in microprocessors, a source of concern in power dissipation may be the leakage process in microprocessors. Therefore, in order to form a microprocessor with reduced-power dissipation, it may be necessary to reduce the leakage power.
Leakage power may be closely related with temperature. As shown in Equation 1 (below), leakage power of a processor may increase proportionally to the exponential temperature.Pleak=Pleak110×Pβ(T-110)  [Equation 1](where, Pleak represents leakage power of a processor, Pleak110 represents leakage power at 110° C. (at the temperature of 110° C., an operation of the processor may be stopped), β represents leakage power coefficient and T represents the current temperature).
Further, in microprocessors with a pipeline structure, an execution unit for executing an actual instruction among components of the microprocessors may be a concern as higher temperature may be achieved when executing instructions among the components of the microprocessors.
FIG. 1 is a block diagram of a conventional microprocessor with the pipeline structure. Referring to FIG. 1, the conventional microprocessor with the pipeline structure may include at least a instruction fetch block 104, a scheduling block 106, a plurality of execution units 108-1, 108-2, 108-3, . . . , 108-n, and a storage unit 110.
The instruction fetch block 104 may execute an instruction fetch function. For example, the instruction fetch block 104 may predict an instruction to be executed next and then previously fetches a pertinent instruction. The scheduling block 106 may select an execution unit for executing a fetched instruction among a plurality of execution units 108-1, 108-2, 108-3, . . . , 108-n and may assign the fetched instruction to the selected execution units 108-1, 108-2, 108-3, . . . , 108-n. The execution units 108-1, 108-2, 108-3, . . . , 108-n may then execute an assigned instruction and may store execution results in the storage unit 110.
However, in the conventional microprocessor of FIG. 1, the scheduling block 106 only decides whether the execution unit will be used or decides not to use the execution unit for executing the fetched instruction. If the execution unit may not be used, that is, an idle state, the scheduling block 106 may assign an instruction. In this case, an execution unit having a relatively high temperature may be assigned in order to execute the current instruction according to the type and frequency of the previous executional instruction. As previously mentioned, temperature may be closely related with leakage power. In other words, leakage power may be proportional to the exponential temperature. Accordingly, in case that an execution unit having a relatively high temperature may be assigned to execute an instruction, there may be unnecessary leakage power.
To reduce this leakage power, various methods have been used recently. For instance, an execution unit may be duplicated, or the leakage power may be reduced by decreasing the temperature of an execution unit by duplicating a pipeline. However, there may be problems associated with the above methods. For example, the dimensions of the microprocessor may be increased and/or the additional power dissipation due to duplication may be unavoidable.